1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly, to a method for manufacturing a cell transistor of a semiconductor memory device, which is able to suppress turn-off leakage current by adjusting the threshold voltage of a cell transistor such as a DRAM or the like.
2. Description of Related Art
Generally, a semiconductor device employing a transistor with a MOS (metal oxide semiconductor) structure creates a short channel effect since the critical dimension of a gate electrode continues to be smaller along with the high integration of the device. To suppress this short channel effect, impurities for threshold voltage adjustment are implanted into a channel region of the transistor, which, however reaches its limit as the integration degree increases.
FIG. 1 is a vertical cross sectional view showing a cell structure of a semiconductor memory device in the prior art. Referring to this, a conventional method for manufacturing a cell transistor with a MOS structure will be described.
Firstly, STI (shallow trench isolation) type device isolation films 12 for defining an active region and a non-active region as a device isolation region are formed on a silicon substrate as a semiconductor substrate 10.
A well ion implantation and an ion implantation processes for threshold voltage (Vt) adjustment are performed on the semiconductor substrate between the device isolation films 12. At this time, in the ion implantation for threshold voltage adjustment, if the cell transistor is a NMOS, a p-type impurity dopant is ion-implanted, and if a PMOS, an n-type impurity dopant is ion-implanted.
And, a silicon oxide film (SiO2) is deposited as a gate insulating film 14 on the entire surface of the semiconductor substrate 10, and a doped polysilicon film 16 and metal silicide (for example, tungsten silicide or the like) 18 are sequentially deposited as a gate conductive film thereon. Then, the metal silicide 18 and the doped polysilicon film 16 are patterned by a photographing and etching process to form gate electrodes.
Continually, a silicon nitride film (Si3N4) is deposited as an insulating material on the entire surface of the substrate where the gate electrodes are formed, and thereafter etched by an overall etchback process, thereby forming space insulating films 20 on sides of the gate electrodes 16 and 18.
Then, a n-type or p-type impurity dopant (for example, P, As, B) is ion-implanted into the semiconductor substrate exposed between the spacer insulating films 20 of the gate electrodes 16 and 18 or between the spacer insulating films 20 and the device isolation films 12, to form source/drain regions 22.
As above, in the method for manufacturing a cell transistor with a MOS structure in the prior art, since channel resistance becomes lower due to a short channel effect with the high integration of a semiconductor device, an ion implantation process is carried out at an increased dose of an impurity dopant for threshold voltage adjustment in order to increase threshold voltage.
However, if the dose of the impurity dopant for threshold voltage adjustment is increased as above, the self-resistance (Rs) and contact resistance (Rc) of the source/drain regions in a narrow surface area become higher, thereby increasing turn-off leakage current. With an increase in the dose of impurity dopants of a threshold voltage adjust region, turn-off leakage current is increased, which makes it difficult for a DRAM or the like to obtain a desired TWR (time of writing recovery) time, and accordingly deteriorates the refresh operation in the DRAM.